Computer Organization and Architecture
What is Computer Organization and Architecture?
A CPU design technique where instruction execution is divided into stages, allowing multiple instructions to be processed concurrently in an overlapped fashion.
Key formula / rule: Ideal Pipeline Throughput
Key points
- Understand the concept of instruction pipelining.
- Identify the different stages of a pipeline.
- Analyze the types and causes of pipeline hazards.
- Explain techniques for hazard mitigation.
Common exam trap
Assuming ideal pipeline performance without considering hazards.
Definitions
- Term
Instruction Pipelining
- Meaning
A CPU design technique where instruction execution is divided into stages, allowing multiple instructions to be processed concurrently in an overlapped fashion.
- Term
Pipeline Hazard
- Meaning
A situation in pipelining that prevents the next instruction from executing during its predicted clock cycle.
- Term
Data Hazard
- Meaning
Occurs when an instruction depends on the result of a previous instruction that is not yet available in the pipeline.
- Term
Control Hazard
- Meaning
Occurs when the processor fetches instructions sequentially, but a branch or jump instruction changes the program flow, making previously fetched instructions irrelevant.
- Term
Structural Hazard
- Meaning
Occurs when two different instructions in the pipeline require the same hardware resource at the same time.
- Term
Forwarding (Bypassing)
- Meaning
A technique to resolve data hazards by sending the result of an instruction directly from the output of one pipeline stage to the input of an earlier stage that needs it, without waiting for it to be written back to the register file.
- Term
Branch Prediction
- Meaning
A technique used to handle control hazards by guessing whether a branch will be taken or not, and speculatively fetching instructions accordingly.
- Term
Pipeline Stall (Bubble)
- Meaning
Inserting dummy clock cycles (NOPs) into the pipeline to resolve hazards, delaying subsequent instructions.
Learning objectives
Understand the concept of instruction pipelining.
Identify the different stages of a pipeline.
Analyze the types and causes of pipeline hazards.
Explain techniques for hazard mitigation.
Calculate performance metrics for pipelined processors.
Formulae
- Name
Ideal Pipeline Throughput
- Note
Achieved only when there are no hazards or stalls.
- Expression
1 instruction / clock cycle
- Name
Pipeline Latency (for one instruction)
- Note
This is the time taken for a single instruction to complete its entire journey.
- Expression
Number of stages * Clock cycle time
- Name
Effective CPI (Cycles Per Instruction)
- Note
Ideal CPI is typically 1 for a pipelined processor. Stall cycles account for hazard resolution.
- Expression
Ideal CPI + Stall Cycles per Instruction
- Name
Speedup
- Note
Theoretical speedup is equal to the number of pipeline stages, but hazards reduce this.
- Expression
Latency of non-pipelined processor / Latency of pipelined processor
- Name
Instruction Throughput
- Note
Measures how many instructions are completed per unit of time.
- Expression
Number of instructions / Total execution time
Prerequisites
Basic computer architecture concepts (CPU, memory, registers).
Instruction Set Architecture (ISA).
Clock cycles and processor timing.
Common mistakes
Assuming ideal pipeline performance without considering hazards.
Underestimating the impact of branch penalties.
Incorrectly calculating the effective CPI (Cycles Per Instruction) with stalls.
Confusing latency with throughput.
Not accounting for the overhead of hazard detection and resolution.
Keywords
Instruction Pipelining
Pipeline Stages
Throughput
Latency
Hazards
Data Hazard
Control Hazard
Structural Hazard
Forwarding
Branch Prediction
Pipeline Stall
CPI
Instruction-Level Parallelism (ILP)
Practice preview
What does the term 'Instruction Set Architecture' (ISA) refer to?…
easy
Which component is responsible for performing arithmetic and logical operations in a computer?…
easy
What is the primary advantage of using cache memory?…
medium